In III-V series compound semiconductor FETs, the frequency band used is increased and accompanying therewith the required gate length is shortened from one-half .mu.m to less than one-half half .mu.m. Therefore, in an FET having a conventionally-used trapezoidal cross-section gate electrode an increase in gate resistance due to a reduction in gate cross-sectional area causes deterioration of FET characteristics. At present, therefore, an FET having a T-shaped gate electrode which a T-shaped cross-section is generally used that enables shortening and fine patterning of the gate length without causing a reduction in the cross-sectional area.
FIG. 11(a) is a plan view illustrating a semiconductor chip including a plurality of FET devices with such T-shaped gate electrodes. FIG. 11(b) is a cross-sectional view taken along line XIb--XIb of FET device mounted on the semiconductor chip shown in FIG. 11(a).
In FIGS. 11(a) and 11(b), reference numeral 200 designates a semiconductor chip including a plurality of FET devices 201, each having a T-shaped gate electrode 211a. Source electrodes 2a and drain electrodes 2b are disposed on the GaAs substrate 1 alternatingly with a predetermined distance L.sub.E (about 3 .mu.m) therebetween. A gate recess 208 having a depth DR of 1000 to 1500 .ANG. and a width WR is located at a predetermined part of each region on the surface of the GaAs substrate 1 between each adjacent source electrode 2a and drain electrode 2b. A gate pad 211b is disposed in the vicinity of the source electrodes 2a and the drain electrodes 2b along the direction of these electrodes.
Fine line patterns 211a extending from the gate pad 211b are disposed at each region between each adjacent source electrode 2a and each drain electrode 2b parallel to these electrodes, and these fine line portions 211a serve as the gate electrodes. Both the source electrode 2a and the drain electrode 2b comprise AuGe alloy, while the gate electrodes 211a and the gate pad 211b is a double-layer structure comprising a lower Ni layer and an upper Al layer.
Both gate electrode 211a and gate pad 211b have a T-shaped cross-section. The gate electrode 211a comprises a gate electrode leg part 211a.sub.1 having a width LG1 smaller than the recess width WR that contacts a bottom surface 208a of the gate recess 208, and a gate electrode head part 211a.sub.2 having a width LG2 larger than the gate recess width WR, as shown in FIG. 11(b). Similarly, the gate pad 211b (not shown in the figure) comprises a leg part and a head part. The width LG1 of the gate electrode leg part 211a.sub.1, equivalent to the gate length, is 0.25 .mu.m. The width LG2 of the gate electrode head part 211a.sub.2 is about 1 .mu.m.
Next, an explanation is given of a method of producing the FET device 201.
FIGS. 12(a) to 12(g) are drawings for explaining main process steps of producing a T-shaped gate electrode employing a conventional double-layer resist method. Each figure illustrates a cross-section of an FET device 201 taken along line XIb--XIb shown in FIG. 11(a).
In the figures, reference numeral 20 designates a resist film exposed by an electron beam (hereinafter referred to as an EB resist film). The resist film 20, having a resist aperture 20a on a part of GaAs substrate 1 where the gate electrode 211a is to be produced, determines a position of a gate electrode leg part 211a.sub.1, and also acts as a mask for producing the gate electrode 211a. Reference numeral 7 designates a resist film exposed by light, such as a resist film for light rays (hereinafter referred to as a photoresist film). The resist film 7 has a resist aperture 7a which is wider than the aperture 20a and includes the aperture 20a of the EB resist film 20 to determine the position of a gate electrode head part 211a.sub.2, and also acts as a mask for producing the gate electrode 211a. An image reversal resist film is adopted as the resist film 7 because the cross-sections of facing opposite surfaces thereof exposed in the aperture 7a are overhanging configurations which are appropriate for being lifted-off.
At first, as shown in FIG. 12(a), a source electrode 2a and a drain electrode 2b each about 3000 .ANG. thick are produced on a GaAs substrate 1 with an interval about 3 .mu.m therebetween, and then an EB resist film 20 is applied to the entire surface in a thickness of about 2000 .ANG. at the flat part thereof on the source and drain electrodes.
Next, a photoresist film 7 is applied to a thickness of about 1.5 .mu.m on the EB resist film 20 as shown in FIG. 12(b). Subsequently, the photoresist film 7 is patterned to form a resist aperture 7a on a part of GaAs substrate 1 where the gate electrode 211a is to be produced as shown in FIG. 12(c). The width L2 of the resist aperture 7a is, for example, about 1 .mu.m, and determines the width of the head part 211a.sub.2 of the gate electrode 211a which is produced in a later process step.
Thereafter, a predetermined portion of the EB resist film 20 exposed in the aperture 7a of the photoresist film 7 is patterned with an electron beam and developed to form an EB resist aperture 20a as shown in FIG. 12(d). Then, the width L1 of the EB resist aperture 20a is 0.25 .mu.m and determines the width of the leg part 211a.sub.1 of the gate electrode 211a, i.e., the gate length of the FET device 201.
The semiconductor substrate 1 is selectively etched with tartaric acid using the EB resist film 20 as a mask to form a gate recess 208 about 1000 to 1500 .ANG. deep as shown in FIG. 12(e).
Next, for example, Ni and Al as gate metals 11 (gate electrode materials), are successively evaporated on the entire surface in the thickness of 1000 .ANG. and 8000 .ANG., respectively, to produce a T-shaped gate electrode 211a in the aperture 7a of the resist film 7 as shown in FIG. 12(f). The position of the gate electrode leg part 211a.sub.1 is determined by the EB resist film 20 and the position of the gate electrode head part 211a.sub.2 is determined by the photoresist film 7.
Finally, the gate electrode materials 11 on the photoresist film 7 are lifted-off by removing the photoresist film 7, and the EB resist film 20 thereunder is removed to complete the FET device 201 as shown in FIG. 12(g).
Here, the height h2 from the recess bottom surface 208a to the lower surface 211a.sub.3 of overhanging portion of the gate electrode head part 211a.sub.2 amounts to a sum of the depth DR of the gate recess 208 and the thickness of the EB resist film 20, that is about 4000 to 4500 .ANG.. This is because, although the EB resist film 20 is applied in the thickness of 2000 .ANG. at the flat portion on the source and drain electrodes, the EB resist film is about 3000 .ANG. thick on a part of the GaAs substrate 1 where the gate electrode 211a is to be disposed due to the level differences between the source and drain electrodes and the substrate.
There is a problem in the conventional T-shaped gate electrode 211a, however, that since the wide gate electrode head part 211a.sub.2 is produced on the narrow gate electrode leg part 211a.sub.1, the gate electrode head part 211a.sub.2 tends to be separated from the leg part 211a.sub.1 when external mechanical force is applied to the head part 211a.sub.2.
In addition, in the conventional method of producing the T-shaped gate electrode, the ratio L1/h2, that is, the ratio of the width L1 of the EB resist aperture 20a, which is almost equal to the gate length LG1, to the height h2, from the recess bottom surface 208a to the lower surface 211a.sub.3 of overhanging portion of the gate electrode head part 211a.sub.2, is restricted. When the ratio is smaller than 1/2, it is difficult to connect the T-shaped gate electrode head part 211a.sub.2 with the leg part 211a.sub.1. Therefore, the conventional process is not applicable to an FET device including a deep recess.
To be more specific, as shown in FIG. 13, in producing an FET device 201 including a deep gate recess 208, when gate electrode materials 11 are evaporated, a gate electrode leg part 210a.sub.1, which is under the surface of the EB resist film 20, is not connected to a gate electrode head part 210a.sub.2, which is placed on the EB resist film 20, so that a T-shaped gate electrode is hardly realized.
Further, although a T-shaped gate electrode can be produced by adopting a thin EB resist film 20 in an FET device including a deep gate recess 208, since the EB resist film 20 is deposited on the entire surface by spin-coating, if the EB resist film is extremely thin, the EB resist film does not completely cover the entire surface, resulting in disadvantages in the production process. In addition, it takes a long time to transcribe a pattern of the gate electrode leg part to the EB resist film 20 with an electron beam, resulting in a low throughput.
Japanese Patent Published Application Hei. 3-145738, discloses a method for producing a semiconductor device including an offset gate in which a gate electrode pattern is transcribed to a WSi thin film and then a gate recess is formed using the patterned WSi thin film as a mask. In this production process of the FET device, although a WSi thin film thinner than the EB resist film is adopted as a patterning mask, the WSi thin film is used as a mask in forming a gate recess while a resist film is used as a mask for producing a gate electrode. Therefore, the production method disclosed in this prior art cannot solve the above-described problem in producing an FET device including a deep gate recess in which a T-shaped gate electrode is formed.